This invention relates to programmable integrated circuit devices—e.g., programmable logic devices (PLDs), and, more particularly, to the use of specialized processing blocks which may be included in such devices to perform large multiplications.
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, the STRATIX® III PLD sold by Altera Corporation, of San Jose, Calif., includes DSP blocks, each of which includes the equivalent of four 18-bit-by-18-bit multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured as two operations each involving two 18-bit-by-18-bit multipliers, or as one larger (36-bit-by 36-bit) multiplier. In addition, one 18-bit-by-18-bit complex multiplication (which decomposes into two 18-bit-by-18-bit multiplication operations for each of the real and imaginary parts) can be performed. Also, up to two individual 18-bit-by-18-bit multiplications can be performed. Moreover, the two members of any pair of multipliers can be configured for multiplications smaller than 18-bit-by-18-bit.
Although such a DSP block may be configured as a multiplier as large as 36-bit-by-36-bit, a user may want to create a larger multiplier. For example, while a 36-bit-by-36-bit multiplier will support 25-bit-by-25-bit single-precision multiplication under the IEEE 754-1985 standard, it is too small for double-precision multiplication, or for 36-bit-by-36-bit complex multiplication. While the multipliers from several DSP blocks can be used together to implement double-precision multiplication, or larger complex multiplication, the logic needed to interconnect the multipliers has heretofore been programmed by the user in the general-purpose programmable logic outside the DSP block, making it slow and less efficient, and consuming general-purpose resources that might be put to other uses. Moreover, such architectures have relied on two or more carry-propagate operations to arrive at the final product, and a carry-propagate adder is a relatively slow adder configuration.